The present invention relates to an interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it, and more particularly, to a method for realizing a inter-column substitution including interleaving/deinterleaving processing apparatus and method and thereof adopt reading media which can read the program, wherein the interleaving/deinterleaving operation processing apparatus and method which is used in error correction generated from a channel environment of mobile communication.
That is, the present invention embodiment the interleaving/deinterleaving, which is essential in realizing CDMA mobile communication system, and using strong application technology for effective and correct signal transfer. Especially, in mobile communication, there generated burst error by multi-channel caused multi-fading. So a codification and an interleaving can make effective transfer by changing a burst error to a random error.
In an international mobile telecommunication-2000 (IMT-2000), an interleaving/deinterleaving processing apparatus is accepted to a transmission time interval (TTI) and an utmost transfer rate is reached to 2 Mbps. At this time, transfer time interval is structured to 10xcx9c80 ms, so assuming that 384 Kbps data rate and 80 ms transfer time interval, then a memory for a first interleaving is reached to 553 Kbits, and if two RAM is used for reading and writing according to a conventional method, a memory which using the interleaving over 1 Mbits and occupied almost whole area of the chip. Moreover, thereof needed a second deinterleaving and a memory for the first and the second interleaving, so memory downsizing is necessary for making high data rate supply modem in one chip.
Another characteristics is performing an inter-column substitute before a block interleaving performing.
In here, refer to the conventional interleaving/deinterleaving structure.
First, in a three memory used structure, one is used for storing input data, another is used for the interleaving/deinterleaving sequence same as for the first memory reading address storing and the other is for storing the interleaving/deinterleaving result.
Second, improving the first structure, instead of storing the interleaving/deinterleaving sequence in the memory, producing an address through a counting machine. This structure uses two memory which divided in two structure following its use; one is uses two memory for storing input data and the interleaving/deinterleaving result, the other uses the memory for reading and writing, in turn.
Third, one memory use structure, reach to the inputted sauce data memory in two-dimension so writes in column direction, reads in column direction and changes the direction in turn.
The first and the second structure are easy in embodiment, but the memory size is fixed from 384 Kbps to 2 Mbps reached high data rate required application, so they are not good for applying in a terminal but the third structure is efficient.
However, in the IMT-2000, the interleaving process method performing inter-column substitution before a simple block interleaving, so simple column and row substitute method cannot complete the process. Because the inter-column substitution need nonlinear structure instead of the two-dimensional structure.
The conventional interleaving/deinterleaving method considers processing timing, and use two memories and during one memory writes input data, the other memory reads storing data. This method has an advantage of obtaining enough processing timing because the memory has small size when a data rate is low. However, considering an increased data and memory size, using two memories is not an advantage any more.
Furthermore, in the IMT-2000 standard, the first interleaver operates to the transfer time interval, up to 80 ms, and to receive this, the memory size has to be larger in proportion to the data rate and transfer time interval. So using two memories is resulted in make a chip to a several or using an outer memory. Therefore, memory size downsizing for the interleaving/deinterleaving to realize one modem to one chip is very important. Furthermore, different from the conventional interleaving performing method, the inter-column is preceded, so when uses one memory in writing and in reading, in column and in row respectively,
To consider the above, performing the interleaving/deinterleaving by using one memory to downsizing the memory size and making one chip modem which can support high data rate needed service is required.
It is, therefore, an object of the present invention to provide an apparatus and a method for processing data burst error correction used an interleaving/deinterleaving, and an address generator to write data in basic read position by generating an address, and using one memory, records the next data thereof, and using channel encoder system to realize it.
In accordance with a first embodiment of the present invention, there is provided an interleaving performing device, including: an interleaving storing unit for sequence storing which is inputted from a writing address generating unit and from a first and a second selecting unit; the writing address generating unit for demanding a memory inter-location offset (WR_OFF) to performing a writing operation in the interleaving storing unit memory block and for generating a practically writing address, data and memory control signal; an address offset generating unit for inputting a middle value (MID_OFF) and a start signal (cal_start) for demand a memory inter-location offset (RD_OFF) from the writing address generating unit, to read in an interleaving sequence and for generating an intermediate variable (COL_OFF) which is used for the memory inter-location offset (RD_OFF) and an inter-column substitution; a reading address generating unit for increasing the address offset generating unit originated signal to as much as a symbol""s memory inter-location offset (RD_OFF) and create an address for reading the interleaving storing unit to generate memory control signal; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operation needed reading operation; and a third selecting unit for selecting appropriate symbol in the memory output signals which are generated from the reading operation, and performed from the reading address generating unit transferred interleaving.
In accordance with a second embodiment of the present invention, there is provided a deinterleaving performing device, including: an deinterleaving storing unit for sequence storing which is inputted from a writing address generating unit and from a first and a second selecting unit; the writing address generating unit for demanding memory an inter-location offset (WR_OFF) to performing a writing operation in the deinterleaving storing unit memory block and for generating practically writing address, data and memory control signal; an address offset generating unit for inputting a middle value (MID_OFF) and a start signal (cal_start) for demand a memory inter-location offset (RD_OFF) from the writing address generating unit, to read in deinterleaving sequence and for generating an intermediate variable (COL_OFF) which is used for a memory inter-location offset (RD_OFF) and an inter-column substitution; a reading address generating unit for increasing the address offset generating unit originated signal to as much as a symbol""s memory inter-location offset (RD_OFF) and create an address for reading the deinterleaving storing unit to generate memory control signal; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operation needed reading operation; and a third selecting unit for selecting appropriate symbol in the memory output signals which are generated from the reading operation, and performed from the reading address generating unit transferred deinterleaving.
In accordance with a third embodiment of the present invention, there is provided a channel encoding system which is using data burst error correction used the interleaving/deinterleaving performing device, including: an encoding unit for encoding inputted sauce""s data column; an interleaving unit for performing inter-column included block interleaving, to the encoding unit transferred data; a modulating unit for modulating block interleaved data through the interleaving unit and transfer it through a channel; a demodulating unit for demodulating the block interleaved data which is modulated through the modulating unit; a deinterleaving unit for performing an inter-column substitution included block deinterleaving to the block interleaved data which is demodulated through the demodulating unit; and a decoding unit for decoding the deinterleaved data by the deinterleaving unit.
In accordance with a forth embodiment of the present invention, there is provided a interleaving performing method for data burst error correction used interleaving performing device, including the steps of: a) storing input sequence of writing address generator, a first and a second multiplexing device; b) obtaining a memory inter-location offset (WR_OFF) in a successively inputted symbol which will be written, and for performing a writing operation in the stored memory block; c) generating a memory inter-location offset (RD_OFF) which is inputting a middle value and a start signal (cal_start) for reading it in an interleaving sequence, and a medium variable (COL_OFF) which is used in an inter-column substitution; d) increasing the generated signal to a successively readable symbol""s memory inter-location""s offset (RD_OFF), and generating memory control signal for reading a stored interleaver RAM; e) choosing a corresponding cycle needed signal between the reading address generator and the writing address generator transferred writing operation needed reading operation and a real interleaving performing needed reading operation""s control signal and address; and f) choosing a corresponding symbol between the memory output signals which are generated by the reading address generator transferred interleaving performing reading operation.
In accordance with a fifth embodiment of the present invention, there is provided a deinterleaving performing method for data burst error correction used deinterleaving performing device, including the steps of: a) storing frame symbol of inputting from a writing address generator, a first and a second multiplexing device; b) obtaining a memory deinter-location offset (WR_OFF) in a successively inputted symbol which will be written, and for performing a writing operation in the stored memory block; c) generating a memory inter-location offset (RD_OFF) which is inputting a middle value and a start signal (cal_start) for reading it in deinterleaving sequence, and a medium variable (COL_OFF) which is used in an inter-column substitution restoration; d) increasing the generated signal to a successively readable symbol""s memory inter-location""s offset (RD_OFF), and generating memory control signal for reading a stored interleaver RAM; e) choosing a corresponding cycle needed signal between the reading address generator and the writing address generator transferred writing operation needed reading operation and a real interleaving performing needed reading operation""s control signal and address; and f) choosing a corresponding symbol between the memory output signals which are generated by the reading address generator transferred deinterleaving performing reading operation.
In accordance with a sixth embodiment of the present invention, there is provided an interleaving/deinterleaving performing method including the steps of: handling an interleaving/deinterleaving performing source data (interleaving)""s frame (block) or an interleaved data (deinterleaving) frame block, storing it in a memory; regarding the storing frame as a former frame, during the interleaving/deinterleaving, the former frame next corresponded symbol is inputted and needs the memory which can store it; and writing according to the previous symbol reading position for the next frame corresponded symbol, without adding the memory.
In accordance with a seventh embodiment of the present invention, there is provided a computer readable recording media including: a first function for correcting burst error of data, using one memory, considering an interleaving sequence followed a read position, for writing next data, in processor possessed interleaving performing device, inputting writing address generator and a first and a second multiplex device, storing an input sequence; a second function for performing a writing operation in a stored memory block, demanding successively inputted symbol used a memory inter-location offset (WR_OFF), generating a real usable address, data, and a memory control signal; a third function for generating an inter-column substitution used medium variable (COL_OFF) and a memory inter-location offset (RD_OFF) for inputting a medium value (MID_OFF) and a start signal (cal_start), and reading it an interleaving sequence; a forth function for increasing the generating signal to as much as a successively readable symbol inter-location""s offset (RD_OFF), and making an address for reading an above stored interleaver RAM, then generating a memory control signal; a fifth function for selecting respectively between the reading operation which is needed for the writing address generator and reading address generator transferred writing operation and a real interleaving performing needed reading operation""s control signal and address; and a sixth function for selecting corresponding symbol between the reading address generator transferred interleaving performing reading operation generated memory output signals.
In accordance with a eighth embodiment of the present invention, there is provided a computer readable recording media including: a first function for correcting a burst error of data, using one memory, considering a deinterleaving sequence followed read position, for writing next data, in processor possessed deinterleaving performing device, inputting a writing address generator and a first and a second multiplex device, storing an input sequence; a second function for performing writing operation in the stored memory block, demanding successively inputted symbol used a memory inter-location offset (WR_OFF), generating a real usable address, data, and a memory control signal; a third function for generating an inter-column substitution restore used a medium variable (COL_OFF) and a memory inter-location offset (RD_OFF) for inputting a medium value (MID_OFF) and a start signal (cal_start), and reading it in a deinterleaving sequence; a forth function for increasing the generating signal to as much as a successively readable symbol inter-location""s offset (RD_OFF), and making an address for reading an above stored deinterleaver RAM, then generating memory control signal; a fifth function for selecting respectively between the reading operation which is needed for the writing address generator and reading address generator transferred writing operation and a real interleaving performing needed reading operation""s control signal and an address; and a sixth function for selecting corresponding symbol between the reading address generator transferred deinterleaving performing reading operation generated memory output signals.
In the present invention, inter-column storing and one memory using structure is basically using one memory following the interleaving/deinterleaving sequence, and considering the inter-column substitution, record next data. Considering following three major points, first, it performed a writing operation according to the reading sequence, so it needs a calculation for the next reading sequence, displacement and for the inter-column substitution restoring used offset. Second, as a method of ensuring the maximum processing timing, speedy and simultaneous operation performable hardware structure is needed. Third, there needs a consideration of data rate changing, that is, changing of an inputted data block size.